(1) Field of the Invention
The present invention relates to a solid-state imaging device and a manufacturing method for the same, in particular to a structure of an image pixel of a MOS-type solid-state imaging device and a forming method thereof.
(2) Description of the Related Art
MOS-type solid-state imaging devices which are used in digital cameras and the like can be driven with a lower power consumption compared to CCD-type solid-state imaging devices. Also, a sensor region of the MOS-type solid-state imaging device and a peripheral circuit region thereof for driving the sensor region can be manufactured based on the same CMOS processing. Thus, their manufacturing processes can be more simplified, and semiconductor devices can be more integrated, compared to the CCD-type solid-state imaging devices. The structure of the conventional MOS-type solid-state imaging devices will be described using an example of an amplification-type MOS-type solid-state imaging device.
As shown in FIG. 1, the sensor region of the MOS-type solid-state imaging device includes a plurality of image pixels 60 (FIG. 1 shows 4 of the image pixels 60). Each image pixel 60 includes a photodiode 61 and 4 transistors (a transmission transistor 62, an amplifier transistor 63, a selection transistor 64, and a reset transistor 65) as its main components.
In the plurality of image pixels 60 that are two-dimensionally arranged along the direction of the paper surface of FIG. 1, gates of the transmission transistors 62 are connected with one another by lines L61. Likewise, gates of reset transistors 65 are connected with one another by lines L62, and gates of selection transistors 64 are connected with one another by lines L63. Also, in the plurality of image pixels 60 two-dimensionally arranged along the direction of the paper surface of FIG. 1, sources of the selection transistors 64 are connected with one another by lines L64.
Among structural components of the image pixel 60 shown in FIG. 1, the transmission transistor 62 and its peripheral regions will be described using FIG. 2A, and the reset transistor 65 and its peripheral regions will be described using FIG. 2B.
As shown in FIG. 2A, at the transmission transistor 62 and the peripheral regions thereof, an n-type signal charge accumulator 602 is formed in a p-well (p-type device formation region) 601 on a semiconductor substrate 600. Also, a p-type surface shield layer 606 and an n-type signal outputter 605 are formed in a vicinity of the surface of the p-well 601. The n-type signal charge accumulator 602 is a component comprising part of a photodiode and accumulates signal charges generated by receiving incident light.
The p-type surface shield layer 606 is formed in an upper area with respect to the n-type signal charge accumulator 602 (the p-well 601 surface side) in order to reduce dark current. The n-type signal outputter 605 is formed away from both the n-type signal charge accumulation 602 and the p-type surface shield layer 606. Also, an insulating layer 603 is formed on a region between the p-type surface shield layer 606 and the n-type signal outputter 605 of the p-well 601. Further, a gate 604 of the transmission transistor 62 for controlling transmission of signal charge is provided on the insulating layer 603. Additionally, the gate 604, the signal outputter 605, and the surface shield layer 606 are covered with an insulating layer 621.
Also, an STI (Shallow Trench Isolation) region 607 is formed adjacent to the surface shield layer 606 (in FIG. 2A, adjacent to the left side of the surface shield layer 606). It should be noted the STI region 607 is formed in regions separating adjacent image pixels 60 and the like.
As shown in FIG. 2B, at the reset transistor 65 and peripheral regions thereof, a source 611 and a drain 612 of the reset transistor 65 are formed apart from each other in a vicinity of one of the surfaces of the p-well 601 formed on the semiconductor substrate 600. Also, the insulating layer 603 is formed above a region between the source 611 and the drain 612 of the semiconductor substrate, and the gate 613 is provided on the insulating layer 603. The source 611, the drain 612, and the gate 613 are covered with the insulating layer 621.
As shown in FIG. 1, in the sensor region of the MOS-type solid-state imaging device, the transistors 62 to 65 of the plurality of image pixels 60 are connected to one another, respectively, by such as the lines L61 to L64. Wiring lengths can be extremely long, and are likely to cause an increase in wiring resistance if the wirings are to be extended to connect with gates and the like. The following describes conventional techniques developed in attempts to solve this problem, with reference to FIG. 3.
As shown in FIG. 3, the conventional MOS-type solid-state imaging devices are structured in such a manner that metal wirings 633a to 633c are provided on each of the gate 604 of the transmission transistor 62 and the gate 613 of the reset transistor 65, and the gates 604 and 613 are connected with the metal wirings 633a and so on with contact plugs 641, respectively. The conventional MOS-type solid-state imaging devices attempt to reduce wiring resistance by adopting such a structure. However, as shown in FIG. 3, an insertion of the metal wirings 633a to 633c causes a problem, that is, an increase in a light path length, a distance D0, from the on-chip lens 631 to the signal charge accumulator 602 via a color filter 632. Since the distance D0 directly affects the sensitivity of the MOS-type solid-state imaging device, with the conventional MOS-type solid-state imaging devices, it is difficult to reduce wiring resistance while also preventing deterioration of the sensitivity. Additionally, as shown in FIG. 3, the sensitivity deteriorates due to a decrease in a light receivable angle θ0 also.
Various attempts have been made to solve the above-mentioned problem. For example, one technique uses a salicide method in laminating a silicide layer on gates, a signal outputter and the like and connects the image pixels 60 with this silicide layer in order to reduce resistance. Another technique attempts to reduce resistance by forming a silicide layer at peripheral circuits with similar use of the salicide method (for examples, see Japanese laid-open patent application publication No. 2001-111022 and Japanese Patent No. 3782297).
However, when adopting the techniques proposed by the above-mentioned documents (Japanese laid-open patent application publication No. 2001-111022 and Japanese Patent No. 3782297), it is difficult to reduce electrical resistance among the image pixels and prevent the deterioration of playback images at the same time. Specifically, with the technique proposed as a first embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022), no silicide layer is formed at a sensor region where image pixels are formed, and thus, wiring resistance cannot be reduced sufficiently. Accordingly, in view of the sensitivity characteristics, it is difficult to adopt the technique proposed as the first embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022).
On the other hand, according to a second embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022) and the other document mentioned above (Japanese Patent No. 3782297), a silicide layer is formed on everything except for a light receiver of a photoelectric converter in a pixel cell, including drains of transmission transistors. Consequently, when adopting the technique proposed by these, leakage current is likely to occur, and thus, noise is likely to occur due to aliasing output from the signal outputter 605.
A junction depth of the signal outputter 605 and the source 611 of the reset transistor 65 is 0.1 [μm] to 0.5 [/μm], and this could be reduced down to approximately 0.05 [μm] to 0.1 [μm] if a pixel size is further miniaturized. Abstracts of 1995 IEEE-IEDM (International Electron Devices Meeting) pp. 449-452 contain a description that cobalt silicide spikes reach a length of 20 [nm] to 100 [nm]. Here, as shown in FIG. 4, a junction between an impurity diffusion layer and a silicon substrate is destroyed due to a cobalt silicide spike, causing leakage current to occur from the impurity diffusion layer to the silicon substrate.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, No. 1, JANUARY 1999 pp. 117-123 contains descriptions on mechanism caused by cobalt silicide, such as that cobalt diffuses from a cobalt silicide layer due to a thermal process, increasing leakage current, and the leakage current value has a distribution within a region, in addition to that the cobalt silicide spikes reach a length of 20 [nm] to 100 [nm].
In other words, according to the techniques proposed by the second embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022) and the other document (Japanese Patent No. 3782297), a silicide layer is laminated on the signal outputter 605 and the source 611 of the reset transistor 65 as well as on the gate 604 of the transmission transistor 62 and the gate 613 of the reset transistor 65. As a result, a metal-semiconductor compound, the component of the silicide layer, penetrates to the p-well (p-type device formation region) 601 or even if it does not penetrate to the p-well 601, it shortens the distance to the p-well 601. Consequently, leakage current increases and has a distribution with in the region.
Due to an increase in the number of pixels for cameras in recent years, when practically used, the signal outputter 605 and the source 611 of the reset transistor 65 electrically connected to the signal outputter 605 are placed in each of several million to ten million pixels in a pixel array. Also, when the peripheral temperature of the several million to ten million sources 611 of the reset transistors 65, which are electrically connected to the several million to ten million of signal outputters 605 and the signal outputters 605, is 60[° C.], leakage current indicates a distribution as shown in FIG. 5 under the condition, for example, that a total area of the signal outputters 605 and the sources 611 of the reset transistors 65 is 0.48[μm2].
FIG. 5 shows a case where a sample time for transmitting a signal downstream for an output to eliminate noise is 4.88 [μsec] and a saturation number of electrons of the signal charge accumulator 602 is 3000. In this case, 90 electrons or more, which approximately account for 3[%] of the saturation number corresponding to a dynamic range of a playback image, that is, image pixels with a leakage current of approximately 300 [fA] or more in the maximum applicable temperature, become visible as a noise in the playback image. As can be seen from the above, the techniques proposed by the second embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022) and the other document mentioned above (Japanese Patent No. 3782297) suffer deterioration of playback images due to leakage current generation as a tradeoff for gaining an advantage of reducing wiring resistance by forming silicide layers.